Jan 20, 2013 #1 C charantejvit Newbie level 3 Joined Jan 18, 2013 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location vellore Activity points 1,296 verilog_ project 36-Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS .pdf 2nbit csa with eac -verilog code please carry save adder (csa) end around carry(eac) ;; charantej.peteti@gmail.com below i posted my project - i have to solve that Attachments 36-Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS .pdf 608.9 KB · Views: 146
verilog_ project 36-Efficient VLSI Implementation of 2n Scaling of Signed Integer in RNS .pdf 2nbit csa with eac -verilog code please carry save adder (csa) end around carry(eac) ;; charantej.peteti@gmail.com below i posted my project - i have to solve that
Jan 21, 2013 #2 joelby Full Member level 4 Joined Jun 6, 2011 Messages 196 Helped 66 Reputation 130 Reaction score 64 Trophy points 1,308 Activity points 2,644 Sounds like an interesting project! Work hard and I'm sure you'll be able to do it.