Effect on max. frequency due to inferred clocks on fpga

[veeraj_patil]

I am synthesizing a design on FPGA .Design has one main clock but it is inferring 2 internal clocks during synthesis. I have constrained the main clock. Do these two inferred clocks affect Max.Frequency of design ?.

 

[mrflibble]

How does it infer that extra clock? How is the extra clock related to the original (main) clock?

 

[FvM]

I also never came across automatic clock inference. Either there's an operation with the clock (gating, inversion) or it has to do with routing restrictions of a specific FPGA family.

 

[mrflibble]

Heheh, yeah, inversion and gating were really also the only things I could think of. But AFAIK it doesn't get reported as a seperate clock (aka taking up an additional clock net), soooooo ???

Mmmmh, actually maybe inversion on an older fpga (without local clock inversion), but I seriously doubt it. Best hear what veeraj_patil has to say about it.

 

[veeraj_patil]

Sorry for the delayed reply. Of the 2 inferred clocks ,one of them(ep5cht/lclk) is generated from a combinational logic (LUT) and the other clock(rdcnt_inferred_clock_9) is derived from ep5cht/lclk through a register. None of the two clocks have any relationship with the main clock(clk_c).So the 2 inferred clocks are not due to inversion or gating.I cant comment whether it is due to routing restrictions, still exploring it ....

 

[TrickyDicky]

Both clocks are poor design. Clocks in FPGAs should never been generated with logic or gated versions of the system clock. This can cause difficulties during timing analysis as the skew can be huge. You should either derrive them through a PLL/DCM (and the timing analyser can then work out their timings from the source clock) or generate clock enables and use the system clock for all internal registers. It will make your life easier and make it easier for the timing analyser.