Hi,
1 - One can also use uncertainty as a further margin after CTS, e.g. to account for the PLL jitter that you don't have control over it at physical design step.
2 - As srideepa said clock uncertainty before CTS can be used to fix setup/hold timing violations, which affect QoR. As most PR tools fix timing violations below/above some thresholds, they may not touch some violations, which may eventually pop-up after CTS. Modifying clock uncertainty may be a good way of fixing these violations "before" CTS, in the expense of adding some more buffers into the design.
Best regards,
Gokhan
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