SPI1_Init_Advanced(_SPI_MASTER_OSC_DIV64, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_LOW, _SPI_LOW_2_HIGH);
Delay_ms(100);
do{
buffer1 = 0;
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS1 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_idle)
break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRSR); //WRSR
SPI1_Write(RDSR_idle); //unprotecting
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS2 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready)
break;
CS = 1;
Delay_ms(400);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRITE); //WRITE
SPI1_Write(ipn1MSB); //ADDRESS MSB
SPI1_Write(ipn1LSB); // LSB
SPI1_Write(0b11000100); //Data
CS = 1; //Deactivate CS
Delay_ms(2000);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS3 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready) break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200); //Activate CS
SPI1_Write(COMM_READ); //READ
SPI1_Write(ipn1MSB); //ADDRESS MSB
SPI1_Write(ipn1LSB); // LSB
buffer1 = SPI1_Read(buffer); //Data
CS = 1; //Deactivate CS
Delay_ms(200);
UART1_Write_Text("buf : \n");
IntToStr(buffer1, buffer2);
UART1_Write_Text(buffer2);
UART1_Write_Text("\n");
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS4 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready) break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRDI); //WRDI
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRDI); //WRDI
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS5 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_idle) break;
CS = 1;
Delay_ms(200);
}while(1);
UART1_Write_Text("\n");
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS1 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_idle)
break;
CS = 1;
Delay_ms(200);
}while(1);
#define CS RD0_bit
unsigned short COMM_WREN = 0b00000110; //Commands
unsigned short COMM_WRDI = 0b00000100;
unsigned short COMM_RDSR = 0b00000101;
unsigned short COMM_WRSR = 0b00000001;
unsigned short COMM_READ = 0b00000011;
unsigned short COMM_WRITE = 0b00000010;
unsigned short ipn1MSB = 0b00000000; //Addresses
unsigned short ipn1LSB = 0b00000000;
unsigned short ipn2MSB = 0b00000000;
unsigned short ipn2LSB = 0b00000000;
unsigned short ipn3MSB = 0b00000000;
unsigned short ipn3LSB = 0b00000000;
unsigned short ipn4MSB = 0b00000000;
unsigned short ipn4LSB = 0b00000000;
unsigned short RDSR_idle = 0b00000000;
unsigned short RDSR_ready = 0b00000010;
unsigned short RDSR_busy = 0b00000011;
unsigned short TEST_result1 = 255;
char TEST_result2[7];
unsigned int buffer1;
char buffer2[7];
SPI1_Init_Advanced(_SPI_MASTER_OSC_DIV64, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_LOW, _SPI_LOW_2_HIGH);
Delay_ms(100);
do{
buffer1 = 0;
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS1 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_idle)
break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRSR); //WRSR
SPI1_Write(RDSR_idle); //unprotecting
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS2 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready)
break;
CS = 1;
Delay_ms(400);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRITE); //WRITE
SPI1_Write(ipn1MSB); //ADDRESS MSB
SPI1_Write(ipn1LSB); // LSB
SPI1_Write(0b11000100); //Data
CS = 1; //Deactivate CS
Delay_ms(2000);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS3 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready) break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200); //Activate CS
SPI1_Write(COMM_READ); //READ
SPI1_Write(ipn1MSB); //ADDRESS MSB
SPI1_Write(ipn1LSB); // LSB
buffer1 = SPI1_Read(buffer); //Data
CS = 1; //Deactivate CS
Delay_ms(200);
UART1_Write_Text("buf : \n");
IntToStr(buffer1, buffer2);
UART1_Write_Text(buffer2);
UART1_Write_Text("\n");
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WREN); //WREN
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS4 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_ready) break;
CS = 1;
Delay_ms(200);
}while(1);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRDI); //WRDI
CS = 1;
Delay_ms(200);
CS = 0;
Delay_ms(200);
SPI1_Write(COMM_WRDI); //WRDI
CS = 1;
Delay_ms(200);
do //test status
{
CS = 0; //Activate CS
Delay_ms(200);
SPI1_Write(COMM_RDSR); //RDSR
TEST_result1 = SPI1_Read(buffer);
ShortToStr(TEST_result1, TEST_result2);
UART1_Write_Text("TS5 : ");
UART1_Write_Text(TEST_result2);
UART1_Write_Text("\n");
if(TEST_result1 == RDSR_idle) break;
CS = 1;
Delay_ms(200);
}while(1);
UART1_Write_Text("\n");
SPI1_Init_Advanced(_SPI_MASTER_OSC_DIV64, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_LOW, _SPI_LOW_2_HIGH);
SPI1_Init_Advanced(_SPI_MASTER_OSC_DIV4, _SPI_DATA_SAMPLE_MIDDLE, _SPI_CLK_IDLE_LOW, _SPI_LOW_2_HIGH);
Do you know that SPI1_Init(); have to be called befor calling SPI1_Init_Advanced(); ?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?