jahanzebanwer
Newbie level 4
I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDIF netlist of my program which is write as a behavioral verilog code. Suppose I write the code (a+b), than I could see in the RTL and Technology schematics that a full-adder has been created inside a LUT but i want to access the EDIF netlist of this RTL diagram created by XIlinx.
Moreover, I learned in the Xilinx Development Reference Guide that the NGD netlist is a logical description of the circuit whereas the NGD netlist Xilinx created for my programs are totally vague. It seems like it is based on the local primitives of the xilinx board but atleast no logical description is available.
Thanks for your time.
Moreover, I learned in the Xilinx Development Reference Guide that the NGD netlist is a logical description of the circuit whereas the NGD netlist Xilinx created for my programs are totally vague. It seems like it is based on the local primitives of the xilinx board but atleast no logical description is available.
Thanks for your time.