edge detection using system generator

[shan14]

Hi
I have an edge detction module implemented in sys gen I have created that model by taking reference of a paper that I fond on net thats why I am not able to understand some part of it
So please help me understand it.
what is the purpose of registers??

also output coming shifted . but when I change the value of virtex2 line buffer to 250 output doesn't come shifted .

where can I get the help for xilinx blockset ??is there any manual?

I have attached the image of model

 

[shaiko]

If that's an "edge detector" - it's probably the most complicated edge detector ever devised by man.

Copying someone's circuit without understanding what it does and why it does that - is the wrong approach towards learning.

What are you trying to design?

 

[FvM]

If that's an "edge detector" - it's probably the most complicated edge detector ever devised by man.

You understand that it's the implementation of an image processing algorithm? I don't know if it's unnecessarily complicated, you need to look at the algorithm details first.

Obviously line buffer size is related to image x size and can't be changed without modifying the design in several places.

I would expect that the working of design is explained in the paper, there are of course user manuals for the DSP system generator, more important is probably a basic understanding of image processing.

 

[shaiko]

I thought that what the OP meant by "edge detection" - is the detection of signal edges.
No mentioning of image processing in the post...

Shan14,
Can you post the original paper?

 

[shan14]

hi
Thanks for reply
This is the original paper

 

[mrflibble]

@shan14:
How good is this canny edge detection compared to other methods? I know what it says in the paper, but papers tend to say their method is awesome. Do you happen to have any other experiences?

 

[shan14]

Hi
This is OK . but output image is coming shifted. I am not able to understand it.
As I mentioned earlier when I decrease the buffer value Output is not coming shifted.

what is the purpose of expression unit of system generator

 

[TrickyDicky]

Hi
This is OK . but output image is coming shifted. I am not able to understand it.
As I mentioned earlier when I decrease the buffer value Output is not coming shifted.

what is the purpose of expression unit of system generator

This sounds like you have some parrallel logic creating some kind of data valid signal, that doesnt have as many pipeline stages as your algorithm.
When you add more stages to the algorithm, you need to register balance the sideband signals.

 

[shan14]

Hi

Its a canny edge detection I am not understanding how they have calculated the Gradient , non maximum supression, thresholding .

How to understand the logic that has been used in the model. I want to understand bit by bit operation, how to start understanding??

 

[D.A.(Tony)Stewart]

Hi
I have an edge detction module implemented in sys gen I have created that model by taking reference of a paper that I fond on net thats why I am not able to understand some part of it
So please help me understand it.
what is the purpose of registers??

also output coming shifted . but when I change the value of virtex2 line buffer to 250 output doesn't come shifted .

where can I get the help for xilinx blockset ??is there any manual?

I have attached the image of model

256> 250? How much shift?

Here is another method of edge detection, using full frame memory, iso-contours on lower grayscale levels which may be more relevant to medical image processing, or any greyscale level decimation.

The quality of any design starts with specifications, rather than generalized terms such as error rate. In this reader's opinion the students failed to deliver this in the paper, which limits its value.

 

[shan14]

Hi

This is what my output comes when line buffer value is 256



This i when line buffer value is 247



I have found this by trial and error method . I am not understanding the buffer. Is it delaying the image???

 

[shan14]

Hi

I am trying to understand this model (image that I posted earlier) but I am not getting anywhere:bang: . please can anybody help me understand this model??
are registers used here for delaying purpose ??

 

[FvM]

Registers always involve a delay of one clock cycle. Thus they are represented as z^-1 elements in the block diagram. Line buffers are delaying by one scan line, so you get pixel information of the previous scan line (1 pixel distance above).

I fear your problem is lack of knowledge both in digital logic design and image processing. No idea how we can help easily.

 

[shan14]

Hi
I want to know In my model of canny How horizontal and vertical component are calculated ???
Because in that model the multiplier, adder and then CORDIC SQRT blocks are there so magnitude are calculated but how the Gx and Gy i.e. Horizontal and vertical component ??????

Also how line buffer works?? suppose I have z^-256 as line size. and input image is 256*256