E1/T1 High Impedance Front End

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Romanp

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t1/e1 impedance

Hi,
Please advice, how should look the system with Quad Falc and 2 work modes.
One mode is the normal E1/T1 interface with corresponding E1/T1 impedances.
Second mode base on disconnection of E1/T1 Falc periferals and connection of high impedance front end.

Thank you
 

t1 impedance


These modes have most of interfaces, it go to high impedance when chip select deactivated. Most problem is input terminators, for input impedance maching.
 

No, I ment something other.
I need to hear E1/T1 signaling without affecting on its amplitude and friquency parameters.
 

Hi,

If I remember well, QuadFalc can be connected in monitoring mode by using two 510 ohms resistors, one on each wire of a 120 ohms twisted pair cable. This correspond to a -20db attenuation. Chip must be put in short haul mode and monitoring must be activated. See chapter 4 of the datasheet. You will find a schematic and all explaination about how to configure the internal registers.

Regards
 

    Romanp

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Romanp said:
No, I ment something other.
I need to hear E1/T1 signaling without affecting on its amplitude and friquency parameters.
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You can use any line interface chip, but without termitator rezistors (or set it high value, if it neading for chip DC mode).
For example Intel LXT388:
The LXT388 differential receivers provide high noise margin for T1/E1 short-haul operation. In
addition, the LXT388 includes two extra receiver/jitter attenuation blocks that can be used for
Driver Performance Monitoring (DPM) in the active channels.
 

I THINK YOU CAN FIND ANY THING ABOUT E1 IN WWW.ITU-T.COM . YOU CAN SIGN UP AND RECEIVE 3 DOCUMENTS .BEFORE , YOU MUST FIND SUITABLE DOCUMENTS FOR YOUR DECIDES .
 

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