E1 Frame and Deframer

[dinesh.4126]

Hi,
I am trying to Implement E1 Frame on VHDL.And code I took from opencore.Has Anybody use that code?
I messed up after seeing that code.
If not can somebody help me to provide assistance so that I can start coding part along with document .
Waiting for Reply

 

[sameh_yassin99]

Hi,

I was going to use the FPGA for E1 Framing and I read the following application note from Xilinx "XAPP868".
However, my manger suggested to use a separate module for E1 framing/deframing for development time saving. So, we used chips from EXAR company.
You may check the link
**broken link removed**

Best Wishes

 

[dinesh.4126]

Thanks For Reply.
Thing is that I downloaded the code from opencore and modify it according to need.But I am not getting exact Idea how incoming frame will be detect and also frame Synchronization.Can you Suggest me some manual From where I get clear picture abut Frame Detection and Frame Synch.

Regards,

 

[sameh_yassin99]

Hello there

Goolge for the standard "CCITT (ITU-T)" and E1 Framing. There are alot of sources and lectures for it.

 

[dinesh.4126]

Please clear doubt
1)In E1 Deframing during Framing Synch. of First Three Frame When Synch. Establish after that we start capturing data from TS1 to TS 15 and TS17 to TS31.Its means we need to skip data of First Three Till Synch. achieved.I am Thinking Right if not assist me.

Regards,

 

[dinesh.4126]

My Doubt is in E1 double frame Format Synchronization be achieved only after receipt of three E1 frames .So in Deframing of E1 will first three Frame contain valid data in TS1 to TS15 and TS17 to TS 31.

Regards,

 

[dinesh.4126]

Synchronization achieved only after receipt of three E1 frames in double frame format.so when synch=1 then only data is valid on the bus.
Its means we start capturing the data from 3rd frame when synch=1 i.e. TS1 to TS15 and TS17 to TS 31 time slots. Am I thinking right.
Please reply.

 

[dinesh.4126]

FPGA Implementation Part :I am using Virtex 2 pro and Having E1 Defarmer code using Double Format and My Doubt is E1 signal is Bipolar but how can I give Bipolar E1 signal to Fpga which has I/O standard in monopolar .I am Attaching the E1 bipolar waveform.
Hope so I cleared My Doubt.

 

[dinesh.4126]

Hello,
In the above post as such Sameh Posted use EXAR chip.
Can we use same chip for clcok-Data recovery.???
To extract the clock from E1 signal .