E as the verification language in comparison with others

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E is the only one?

hi can anybody send the system verilog learning matirials.
 

E is the only one?

search "system verilog",you can find them
 

E is the only one?

sv is your better choice
 

Re: E is the only one?

hi
can anybody help me. my question is, while doing eVC with eRM methodology we r using sequences for stimulus generation and If we r not using eRM methodology then how can we generate stimulus? can anybody give me brief about it.
 

Re: E is the only one?

Hi,

Specman is used to write e code and check the design which is of cadence.


NC-Sim of cadence can be used to write code and check the design in Verilog, VHDL.



Both Specman and NC-Sim can be interfaced to verify the DUT.


 

Re: E is the only one?

Not only with NC ,U can also use VCS and Modelsim with Specman.
 

Re: E is the only one?

Specman is the environment for language "e" and its from cadence. whereas system verilog is from synopsys. it uses for both design as well as verification purpose. No doubt, more and more people are migrating toward the SV but still e language has its own slot in the industry... so both will exist...
 

Re: E is the only one?

SystemVerilog now is supported by Cadence, Mentor Graphics and Synopsys
It can be used for design purposes too
More and more tools are supporting SV and lots of people migrate to it since it can be used also for design
also it's becoming more popular than SystemC

read interesting articles here about SystemVerilog:

**broken link removed**
 

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