Dynamic Phase Alignment with Virtex 4

[alzomor]

Hi

We are using virtex 4 FPGA , we are using it's LVDS to inteface to Tigersharc linkport
The linkport is operating at 125Mhz DDR.
My Question is:
Do we need to use the Dynamic Phase Alignment available on ISERDES modules of Virtex 4 ? or we can just the simple mode of ISERDES without DPA and still getting correct Data?

Salam
Hossam Alzomor
www(.)i-g(.)org

 

[vlsi_whiz]

Well, to connect the TigerSHARC link ports to FPGA,you first need to do the LVDS Tx and Rx modules. The Tx module can be done using the LVDS Tx function or by using the DDR IO. With link port clocks you need to align the data with the clock since data will be clocked at both the rising and falling edges of the link port clock. I suggest you align the data with the clock while transmitting LVDS data. If the SERDES in the FPGA has the data alignment option use it to align the data to the LVDS clock.

I'm doing the same thing with the Altera Cyclone series. Though these FPGA's don't have SERDES built into them, I generate the LVDS Tx and Rx using DDR IO and then connect them to the TigerSHARCs on one side and SERDES on the other.

 

[alzomor]

Hi

1st thank you for your reply.
TS already aligns the data when transmitting it.
also ISERDES hade a LVDS input within it.
I think you get my question wrong , I may be explained t in a wrong way.
My question again is:

IS it important at the receive side to use the bitslip and DPA to compensate for jitter and skew introduced on the bus?

Salam
Hossam Alzomor
www(.)i-g(.)org

 

[vlsi_whiz]

IF the serdes has linkport/lvds interface, you need not use the phase alignment. Plus the TS takes care of that. So you need not do DPA when connecting link port to Serdes.

 

[alzomor]

Dear VLSI_WHIZ

Thanks again for your interest in answering me.
But I think the matter is not that simple because in simple application notes of Xilinx
They used the BITSLIP and DPA with there LVDS interface and it's implemented within the SERDES module.
To decide to use it or not depends on the frequency , length of the link and quality of cable or traces between FPGA and TS.
My question is at what frequency should we use DPA
at after what length

Salam
Hossam Alzomor
www(.)i-g(.)org