Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Dynamic Comparator offset

Status
Not open for further replies.

GauthamG

Newbie level 3
Newbie level 3
Joined
Mar 4, 2014
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
23
Hi all
Can anyone tell me how delaying of a clock in a dynamic comparator makes its performance better??
also
How the offset is reduced in a dynamic comparator by delaying the clock???
 

Delayed, relative to what?

If the input signal is "busy" and changing in lockstep
with (say) a sample clock and a time-offset comparator
clock, there is certainly a "sweet spot" that gives you
the best settling time vs sample droop vs max digitization
rate compromise.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top