dynamic comparator and DAC in pipelined ADC

[tyd]

I am just a begineer in analog circuit design.I need help for dynamic comparator in pipelined ADC.I have two DAC which is connected to ADC which composed of two dynamic comparators. Whe I test them seperately,they works fine.But when I connect DAC to ADC, the output from one DAC is not correct.I search papers about this problem.It says it is due to loading effect. The input capacitance should be increased.I try this way,but it doesn't work. The ouput from another DAC workd fine when I connected it to ADC.But the problem is it needs one clock cycle to get ouput.I want to get the ouput half clock cycle for each stage.I hope I can get suggestions about this.Thank you so much for your help.

Added after 1 hours 2 minutes:

I forgot to mention in my question that I use basic latch comparator in sub-ADC.I tried to put two interters at the end of ADC for first case.It doean't work. Buw when I put ideal buffer(vcvs in cadence) between sub-ADC and sub-DAC.It workd fine. How do I replace that ideal burrer with simple trnasistor level circuit.

Thanks so much for your help.

 

[ocarnu]

As I understand it might be o problem of undersizing the transistors driving the capacitance. Make W/L larger.

 

[tyd]

Thank you for your help.But it seems that I need to decrease the size of input capacitance.

 

[sunking]

and you can find a good comp. from the paper on this board