Dual vs Triple synchronizer on FPGA input

[shaiko]

When is it worthwhile considering Triple DFF synchronizers on FPGA inputs instead of the commonly used Dual DFF ?

 

[sureshaa]

Dual DFF itself enough to remove the meta stability when CDC happens. I dont about Triple DFF synchronizers.May be the below link will give proper justification for why dual DFF is enough for sync.
https://www.google.co.in/url?sa=t&r...McjnxHA6ZRNgk0pN7XKPc-w&bvm=bv.42965579,d.bmk

 

[TrickyDicky]

Dual will always give you a 1 or a 0. I only use triple when I need to do edge detection, or data alignment.

 

[shaiko]

What if the metastability isn't settled for a full clock T and proceeds to the second DFF ?

 

[TrickyDicky]

From my understanding, the only problem is the first FF sampling during a transition of the IP, and it can go metastable. The 2nd FF should never sample an edge, so will always flip to 0 or 1, even if the first FF is metastable.

 

[shaiko]

The 2nd FF should never sample an edge, so will always flip to 0 or 1, even if the first FF is metastable.

You assume that the metastability condition is resolved befor the second clock edge arrives. But what if we are working at a very high frequency and the metastability condition doesn't have enough time to resolve - causing setup time violations?

 

[std_match]

It is not possible to guarantee that metastability problems are avoided.
The MTBF for a circuit can be calculated, and you add synchronizer stages if you want to increase it.

From Altera handbook 12.1, Volume 1, chapter 14:

"Designers commonly use two registers in a synchronization chain to minimize the
occurrence of metastable events, and a standard of three registers provides better
metastability protection. However, synchronization chains with two or even three
registers may not be enough to produce a high enough MTBF when the design runs at
high clock and data frequencies."