Dual power supply buffer vs single supply buffer + pull ups?

[brisk]

Hi, I am working on an ARM JTAG design. I plan to use FT2232H as the chip.

On the JTAG side, I am considering to use SN74LVC07A for the buffer.

FT2232H uses 3.3v as Vcc, so I am going to give 3.3v to SN74LVC07A. As for JTAG header side, I am using pull up resistors to connect to the Vref so I can connect the jtag to different system. (1.6v-5.5v)

However I was suggested to use dual power supply buffer, e.g, SN74AVC2T45.

I am wondering besides the cost, what are other differences?

Is there any advantage to use dual power supply buffer SN74AVC2T45 over single supply SN74LVC07A plus pull ups?

What about speed?

Thanks

 

[kender]

Re: Dual power supply buffer vs single supply buffer + pull

What about speed?

I would go with a dual supply buffer, because I think is can work at higher rates.

Let's take a look at the pull-up variant. During high-to-low transition the drain-source resistance resistance of the FET (R_DS_ON) becomes small - on the order of few Ohms. R_DS_ON and the capacitance of the line have an RC constant, which limits the speed. Similar situation would occur in the double supply buffer. But this is not the biggest limitation. During low-to-high transition the pull-up resistance (probably on the order of 1kΩ ) and the line capacitance have another bigger RC constant. The value of the pull-up can't be arbitrarily low, because the buffer should be able to pull the line below the logic-low threshold.

 

[brisk]

Re: Dual power supply buffer vs single supply buffer + pull

Thank you. FT2232H's clock is 30MHz, will this have significant impact on the speed? Let's say I use 20K resistor for the pull ups.

thanks

What about speed?

I would go with a dual supply buffer, because I think is can work at higher rates.

Let's take a look at the pull-up variant. During high-to-low transition the drain-source resistance resistance of the FET (R_DS_ON) becomes small - on the order of few Ohms. R_DS_ON and the capacitance of the line have an RC constant, which limits the speed. Similar situation would occur in the double supply buffer. But this is not the biggest limitation. During low-to-high transition the pull-up resistance (probably on the order of 1kΩ ) and the line capacitance have another bigger RC constant. The value of the pull-up can't be arbitrarily low, because the buffer should be able to pull the line below the logic-low threshold.