brisk said:
I would go with a dual supply buffer, because I think is can work at higher rates.
Let's take a look at the pull-up variant. During high-to-low transition the drain-source resistance resistance of the FET (R_DS_ON) becomes small - on the order of few Ohms. R_DS_ON and the capacitance of the line have an RC constant, which limits the speed. Similar situation would occur in the double supply buffer. But this is not the biggest limitation. During low-to-high transition the pull-up resistance (probably on the order of 1kΩ ) and the line capacitance have another bigger RC constant. The value of the pull-up can't be arbitrarily low, because the buffer should be able to pull the line below the logic-low threshold.