akeedthe
Junior Member level 1
Hi All,
Im trying to come up with a Dual Port Distributed RAM - one made using the Xilinx IP Core and test it against one made by me from scratch.
Ive followed some of the example code given by Xilinx (for my own)
But specially in the IP Core I tried as attached files of my toplevel and testbench. Im confused between what I get on the SPO and DPO port.
Please advice.
PS- append the .txt files back to .vhd to open
Im trying to come up with a Dual Port Distributed RAM - one made using the Xilinx IP Core and test it against one made by me from scratch.
Ive followed some of the example code given by Xilinx (for my own)
But specially in the IP Core I tried as attached files of my toplevel and testbench. Im confused between what I get on the SPO and DPO port.
Please advice.
PS- append the .txt files back to .vhd to open