Driving capacitive load with CMOS inverter buffer.

[imrankhanPNU]

Hello,
How to calculate the number of (CMOS inverter) buffer stages to drive capacitive load? In my case, I am driving a 1nF capacitive load with CMOS (inverter) buffer with the digital signal having an amplitude of 0-5V, and 1Mhz frequency.

Thanks.

 

[betwixt]

Very difficult to say exactly because a loaded CMOS inverter won't switch exactly 0V to 5V but consider that a 1nF capacitive load presents Xc of 159 Ohms at 1MHz and you may have additional loading by other circuits. You will get some idea by looking at the appropriate data sheet and output voltages under different current loads. A single buffer would have to produce full voltage at more than 32mA. It isn't usually a good idea to apply capacitive loads directly at CMOS outputs, especially logic gates because the peak charging and discharging currents will be considerably higher.

Brian.

 

[KlausST]

It isn't usually a good idea to apply capacitive loads directly at CMOS outputs, especially logic gates because

.. it violates logic gate max output current specification.

Klaus

 

[dick_freebird]

There's a trade-space here, with taper factor vs speed and
edge rates desired. You also will want to step away from
simpleminded inverter strings, to make a "break before make"
behavior in the final and some predriver stages, as
shoot-through currents can be substantial dynamic Idd
contributors.

You would design interconnect, device width, thermal
considerations based on max load, max freq, max supply,
max temp on both a time-averaged and peak-current
reliability constraints.

 

[crutschow]

Also depends upon how fast you need to charge and discharge the capacitance.

What logic buffers are you using?

The gate dissipation to drive that capacitance at 1MHz is only 25mW, so that should not be a factor.

 

[Easy peasy]

consider a mosfet gate driver chip which is designed for exactly this type of thing