Drive 3.3V part with 2.5V?

[digi001]

I am looking to use this part at 3.3V

sn74lvc138a
https://www.ti.com/lit/ds/symlink/sn74lvc138a.pdf

A,B,and C inputs will be 3.3V, however one of the enable inputs 'G2A' to this IC is only 2.5V. The datasheet shows a min V_IH of 2V. Is this ok for a reliable design or should this signal 'G2A' be translated first to 3.3V?

 

[D.A.(Tony)Stewart]

The question is how much margin do you need, is a function of EMC noise ingress.
A pull-up R is not recommended ,but I think you can terminate with pull-up down to 3V without overloading output but lowering impedance enough for noise margin. Consider 1mA.

So R2/(R1+R2)3.3 = 3.0V
and 3.3V/ (R1+R2) <= .5mA
Solve. R2= 220Ω pullup R1≈ 1K8Ω to gnd. to avoid spurious behaviour of latchup. (See CMOS app notes for better choice or explanation.)
If any chance 2.5V port has no Vcc when 3.3 is on , do not consider this to avoid SCR effect. If same Vcc , disregard.

 

[digi001]

So your saying a pull up resistor to 3.3V on the 2.5V signal would help this?

 

[D.A.(Tony)Stewart]

NO I said" A pull-up R is not recommended "

but a pullup and pulldown biased below Vdd such as 3.0 on 3.3 Vdd would improve noise immunity.

 

[digi001]

Ok i understand. So NOT a 'pull-up' but rather a' pull-up and pull-down' to 3.0V. Well I don't have 3.0V on this board but i can look into this. What would be wrong with a pull up to 3.3V?

So basically with adding the pull and pull-down current of the signal increases and improves noise immunity? (should these resistors be located at the input to the encoder, or location doesnt matter)

Any elaboration/reasons behind your recommendations would be great. Can you explain SCR effect?

 

[D.A.(Tony)Stewart]

the 220 or 200Ω pullup increases VinH margin at the expense of VinL and risks non-linear behavior driving CMOS inputs greater than Vdd if capacitance on input. SCR or silicon controlled rectifier is the SCR effect of PNPN vertical junction on all CMOS devices and can be catastrophic for higher Vdd with low ESR shunt across Vdd and Vss.. It requires power cycle to remove effect if device does not get too hot. Normally not a concern unless you drive higher than Vdd, and pullup is has shunt capacitance which can cause "adverse effects." research CMOS app notes on SCR failure modes and pull-up recommendation is NOT advised. However we are applying a termination voltage Thevanin equivalent voltage of 3V with the R1+R2 divider load on source of 2.5V on chip with 3.3V input. so VoL increases a bit and VoH increases resulting in more even voltage or impedance noise power immunity from stray E field impulses on signal path. Depending on your layout, is short on ground plane. It may be adequate to do nothing as 2.5 exceeds minimum requirement at nominal but perhaps not at worst case temp and supply for both source and destination. If they share a common Vdd. no problem...