Drill into the DRC deck and see what defines "chip edge".
It may not be prBoundary. Might be "bulk" or "scribe" or
something like that.
First step to debugging is understanding what the rule
is supposed to be telling you. Do not assume developer
clarity or communications skills, flowed all the way to the
error report line nor that you're imagining their meaning
as meant.
Thank you for the fast reply. I pulled up the DRC deck and am looking through it.
Are those key words to look for?
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I found these lines within DRC that are used to define the chip, I believe. ChipWindowUsed is not currently defined.
There is list of EXTENT layers that get mapped to the MT_LAYERS but do not know which extent layer to used. They seem to be defined from physical layers.
I start with searching the error text, to find the rule code; then follow the logic backwards through the deck until you can identify the layer precursors that make the logical args.