This would be a technology-specific rule and can
depend on the specific transistor's geometry as the
distance-to-tap rule works on the entire active area
(not edge:edge). Tap rule may end up being the
last constraint on device W and L, when a tap can
no longer be placed to "access" the innermost active
area within rule length.
You should look to your foundry PDK design rules
(doc, or parse the script file) for this technology
specific stuff.
This would be a technology-specific rule and can
depend on the specific transistor's geometry as the
distance-to-tap rule works on the entire active area
(not edge:edge). Tap rule may end up being the
last constraint on device W and L, when a tap can
no longer be placed to "access" the innermost active
area within rule length.
You should look to your foundry PDK design rules
(doc, or parse the script file) for this technology
specific stuff.