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DRC Rule for Well Tap cells

ApTuPr

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Hello Folks

What is the minimum cell interval for placing well tap and tie cells in Innovus?

I need help ASAP!! :)

Thanks in advance
 

dick_freebird

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This would be a technology-specific rule and can
depend on the specific transistor's geometry as the
distance-to-tap rule works on the entire active area
(not edge:edge). Tap rule may end up being the
last constraint on device W and L, when a tap can
no longer be placed to "access" the innermost active
area within rule length.

You should look to your foundry PDK design rules
(doc, or parse the script file) for this technology
specific stuff.
 

ApTuPr

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This would be a technology-specific rule and can
depend on the specific transistor's geometry as the
distance-to-tap rule works on the entire active area
(not edge:edge). Tap rule may end up being the
last constraint on device W and L, when a tap can
no longer be placed to "access" the innermost active
area within rule length.

You should look to your foundry PDK design rules
(doc, or parse the script file) for this technology
specific stuff.

Thanks a ton dick_freebird for your info. Will definitely look into it and revert back if in case didn't understood anything.
 

ThisIsNotSam

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the documentation that comes with the standard cell library is likely to also contain this explanation.
 

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