bdatta
Newbie level 4
Hello All
I am starting with the layout of my system using 45nm IBM-SOI models provided by MOSIS. I am using Calibre to do DRC/LVS & using the rule-decks provided by IBM. For the simple inverter i am consistently getting the following 2 errors. All other errors can be eliminated by judiciously following the design rules stated in the manual but there's little info on the errors i am getting. Any help will be greatly appreciated:
1. GR10Bx43pd_UA: UA min predicted density (%) with 100 micron tiling > =10 within density_window
2. GR10Bx43pd_UB: UB min predicted density (%) with 100 micron tiling > =10 within density_window
I realize that this has got something to do with the pattern density of my layout but my transistors are as close to each other as possible & I have no clue as to what element to add to increase the pattern density.
I am starting with the layout of my system using 45nm IBM-SOI models provided by MOSIS. I am using Calibre to do DRC/LVS & using the rule-decks provided by IBM. For the simple inverter i am consistently getting the following 2 errors. All other errors can be eliminated by judiciously following the design rules stated in the manual but there's little info on the errors i am getting. Any help will be greatly appreciated:
1. GR10Bx43pd_UA: UA min predicted density (%) with 100 micron tiling > =10 within density_window
2. GR10Bx43pd_UB: UB min predicted density (%) with 100 micron tiling > =10 within density_window
I realize that this has got something to do with the pattern density of my layout but my transistors are as close to each other as possible & I have no clue as to what element to add to increase the pattern density.