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[SOLVED] [DRC error] GR131_top: Ratio of metal area to Gate area error

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Member level 5
Jan 8, 2014
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I have an error of DRC (calibre DRC, ibm CMRF7SF pdk, Cadence IC615):

GR131_top: All (Gates not over TG) must meet the ratio of AM metal area to {(PC over RX oxide area) + 10 x (diode diffusion area)} <=150.

- I created a core layout. I pass DRC of core layout.
- I added the I/O Pads and the error occured.
- I removed the connection of AM metal to the core circuit, but error still happened.

2015-04-26 1-06-21 PM.png

Does anyone have experience about this? Please help.

- I removed the connection of AM metal to the core circuit, but error still happened.

I can't tell you why the error didn't disappear, but why not spring for (a pair of) protection diodes close to the gate inputs?

It's possible that there is some rules logic that looks for pad-cut
(silox, whatever) and then enables I/O and antenna rules for
chip level signoff completeness. You could read the rules deck
and dope that out. The rule looks like an antenna rule, which I
am seeing a distinct rules-set for in my current foundry. Maybe
yours has an all-in-one, but modal based on content, setup.

Look to the detailed result, which should highlight a net (or nets)
which offend. Measure the metal area and the gate area and
satisfy yourself that the rules logic is being triggered. If so then
consider the usual antenna strategies - breaking and via-jumper-
re-connecting the metal trace, using an antenna diode to fix it,
whatever your options may be. I'd recommend searching through
the foundry PDK docs for "antenna" to see what they have for
you, in this vein.

Thank to erikl and dick_freebird,

Now I knew the problem is the pad which connected to nMOS current source (even though it is connected via a poly resistor!). We have to increase the nMOS device size. Or we connect the pad to a floating MOS (to increase diode diffusion area) to pass DRC error and I will cut the connection before I measure it.

@ erikl: I also use ESD diodes connect to that net. This solution also increases the diffusion area, but I don't know why the error still happens.

A poly resistor will not help Met1 antenna charging. I have
seen some antenna rules sets which are dumb and treat
a resistor as a line-break but this is not physically proper.
Nonetheless I have taken advantage of such "cheats" for
things like supply decoupling MOS caps which flag for the
huge supply net periphery (never mind that these nets
are very junction-shunted, the same rules were also too
dumb to comprehend that). As simple as putting a
'resistor' polygon across a poly stub for the gate connection
and the whining ceases. But this is case by case, rules

If you understand the rules logic then maybe something
in this vein will occur to you (just think about the real
vs the rule, before you decide to take advantage of the

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