drawing bulk in layout of transistors

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perado

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I want to draw layout for my circuit in L-edit that has NMOS and PMOS transisors is it important to draw bulk area for this?
beacuse i see some layout that doesnt have bulk area, is it true or no?
 

the required cad layers depend on the process and on the PDK, in most CMOS processes bulk is not drawn
 

I use L-edit and use the generic(default) layers in it ( not special PDK) if I dont draw bulk area for transistors then how I calculate the layout area(chip area) ?
 

once again the chip area definition is very process dependent, in some cases it has to include the seal ring in other it is just defined by a minimum enclosure to pads, in other cases it requires adding a special recognition layer at the top level. It does not have much to do with NMOS definition or device recogniton layers
 

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