DRAM design and simulation

[digital design]

Hi all,
I am trying to simulate a DRAM cell using Cadence. I create the DRAM cell that consist of a transistor and a capacitor. Large DRAMs are divided into multiple subarrays. There are some wordlines and bitlines in the subarray for controlling write and read mechanism.
I have studied VLSI book of Weste and Harris but I need to help for designing row and column circuitry. I can`t find a way to set an initial charge on the capacitor. I can't find out how must I read and write data?!
I got a sense amp and a decoder going and they work.
Any one have any experience with simulation of DRAM cells?
Can any one introduce a reference to me?

 

[leon30]

Hello there,
First, there should be a way to set the initial condition of the capacitor, it should be abbreviated some like 'IC' in the properties if the device, and should denote the precharged voltage across the capcitor, but it depends on the model you're using. The ideal model found in analogLib -> cap should have it. Can you post a pic on the whole properties window of your capacitor?
Second there are generally two ways of simulating digital circuitry in Cadence IC design framework. The first is to use digital simulator, but that depends of whether you have one in your package or not. The second one is to use ordinary transient simulation. In my opinion this is the better option because it gives you better information about delay and signal waveform (distortions, noise, etc.). To generate digital sequence (for clock/input/read/write signals) you can use vpwm ideal periodic voltage source in analogLib and you can 'correct' its ideal properties with adding a real buffer stage (or 2 NOT gates) right after the source, and before your circuitry. Also you can achieve more realistic conditions with adding delay to the power source and then ramp it up to its stable value, then switch on the clock, and finally sending data to the inputs (read/write operations).

 

[digital design]

Many thanks for your help
I use ordinary transient simulation and vpwl or vpulse voltage source to generate digital sequence. I use tsmc's library. I need to help to design control logic( for reading and writing ). Can you help me in this way? or introduce a reference?

 

[leon30]

Well,
**broken link removed** is some very nice reference but it is for SRAM and in french, but if you add it to the wiki article about dram operation here you could easily make the control logic of the bit and word lines, also you can have a look at these two programs and the build-in examples - 'microwind' and 'dsch', they were used for education at my university so they should be useful and I know for sure there is example of DRAM. Also you can see the books who use these programs **broken link removed**, probably the second one ~Advanced CMOS Cell Design.

 

[digital design]

Many thanks for your help.