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DRAM and BRAM : how to declare in VHDL

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tahtouh

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hello

i want to knwo how to declare a DRAM, in VHDL, how to access to it and the time diagram, if it is synchronous or asynchrounous

if there are any reference or doc,

can any one help me please

thank's
 

syedshan

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If you mean to say Distributed RAM by DRAM and Block RAM by BRAM in Xilinx FPGAs, then you can find it in ISE language template.
In ISE, goto Edit menu -> language template -> VHDL -> synthesis Constructs -> RAM and there you find those.

Hope this is what you meant
 

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