Hi... Is the drain diffusion capacitace due to overlap of the gate on the drain, how is this capacitance different from the diffusion capacitance in the case of a diode, wherein the capacitance is due to the minority carriers on the neutral regions... but in case of the MOS there is possibilty of only one type of charge carriers to diffuse, then how come there is a diffusion capacitance...?
defussion is any space or sector charge of an insector realm
being relative to another
and this includes thru packaging and substrate to ground
via coupling to another section that is relative also to ground
so closing a charge region
in terms of simulated gates this is transparent mostly
but to the engine used
and in most design is definable
remember equal and opposite reactions also set up charge regions
and these act as capacitors
The capacitance due to the overlap of gate over source/drain is called Overlap Capacitance.
The drain/source diffusion capacitance is like the diodo difusion capacitance because it is formed in a inverse biased P-N junction (drain/source to substrate).
Like the diodo, the capacitance varies with the voltage across the junction.
The picture show the capacitance vs. voltage behavior.