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Drain Current drift in LDMOS Class AB Power Amplifier

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palanisamy2k

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Hi,

I'm working with L-Band ClassAB power amplifier. I have designed a power amplifier using Freescale LDMOS. While testing the amplifier works fine upto 200W ( design is for 1000W peak power at 2uS ( 2% Duty cycle)). After the output power Exceeds 200W the drain current suddenly reduced to zero. I have tried with another device. But same story repeats. I couldn,t identify the reasons. Can any one help on this?...

Thanks in advance.
 

vfone

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Maybe somewhere in the schematic is a thermal protection which needs adjustment..
 

palanisamy2k

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Maybe somewhere in the schematic is a thermal protection which needs adjustment..
Thanks for your reply. I am not included any thermal protection here. But, i am using Only one part of the MRF device for tuning. ( It has two gate and drain). I decided to tune each section individually. But got failed. The second section also got failed as the first one.

Please advice.

Thanks
 

FvM

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You report isn't quite clear. You mean, that the output transistors got destroyed in the test?
 

palanisamy2k

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FvM..

Yes. While testing, It is working fine upto 200W. Then suddenly the drain current drifts to zero. I found that the Gate is shorted.
 

vfone

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If the transistor get burned is a different story. Most probably you get ruggedness problem due to high VSWR and may need to investigate this issue.
Investigate also the bias current change over RF input power, and thermal behavior at high power.
Another common problem in high power LDMOS amplifiers is the quality of the output capacitors. If they fail at high peak voltages, the transistor get damaged.
 

palanisamy2k

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Actually the LDMOS device (MRF6VP121KH) is Pushpull transistor. The device is capable of delivering 1000W of output power( 2X 500W device in a single package). We planned to test each side seperately sothat each side can be tuned seperately without affecting the other side.

But during testing, the device got failed at approximately 250 watts of output power (Expected >500Watts).

The gate is showing short circuit. The output is connected to an attenuator with >30dB return loss. The output capacitor is also 500V capacitor from Johanson for RF application and is working fine.

We measured the temperature of the device. It was <35degC during the testing. The device mounting and thermal dissipation was perfect. The device failed within a fraction of second when the output power is ~250Watts. If thermal dissipation is the problem, the temparuture of the device must be exceeded. but, assuming 40deg difference between chip and thermal sensor, it was only 75 degree which is well below the limit of >200degC . Also the duty cycle was 1% only at 32uS pulse width. So, there was enough time for cooling between pulses.
 

FvM

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In a short, you're saying this shouldn't happen. Of course. So either there's a quality problem with the transistors, possible but unlikely, I think. Or you have a hidden problem in your circuit. vfone addressed some possible cases, but their are most likely more. GD shorts are mostly observed after causing a breakdown.
 

BigBoss

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Some hidden peaks due to inductive loading effect of gate line can be cause.Normally you can't observe this overshoots but a high accuracy oscilloscope...
I think the gate is overdriven with some overshooted peaks...
 

palanisamy2k

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I think the gate is overdriven with some overshooted peaks...
Hi BigBoss,

I have biased the gate with 1Kohm series resistor and not with Inductive feed. Is there any possibility of overshoot? If so please suggest me a method to overcome this problem.

Thank you.
 

FvM

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I fear, it's effectively impossible to determine the reason for circuit/device failure from a distance, except for possibly giving some hints.

You have clarified, the load impedance can't be a problem in the setup. What else? Are you sure about the reliable operation of the pulsed signal generator and the bias source? Preferably, you would record an ouput power and supply current signal during the test up to the failure event.

How about the circuit layout? Does it follow the Freescale reference design? Are you sure that it can't start self-sustained oscillations above a certain input power level due to unwanted feedback pathes?
 

palanisamy2k

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Hello FvM,
Thanks for your feedback.
The layout is not the one that is recommended by freescale. The reason is, we want to reduce the size. So, we decided to go with 10.2 dielectric instead of 2.55 dielectric recommended by freescale. Using agilent ADS, we generated the layout for the impedance given in the datasheet for the operating frequency.
We also have the suspection that, the failure could be due to oscilations. Is there any way to avoid this? How to confirm this?

---------- Post added at 08:01 ---------- Previous post was at 07:51 ----------

After power ON, I terminated the input and measured the output in the spectrum analyzer for any spurious oscillations. But, nothing was visible. Also, when the output power was less than 200W , there were no oscillations observed from 50Mhz to 2GHz except the signal at 1030MHz. So, I thought that there was no oscillations and proceeded further by increasing the input power by 1dB where the failure happened (within a fraction of a second) . We observed a spark nearer to the drain side. After that there was no drain current, and the gate was showing short circuit.
By opening the failed device, We observed a burn nearer to the drain Pin and all the wire bonding has been burnt.

---------- Post added at 08:03 ---------- Previous post was at 08:01 ----------

If you want to see the photograph of the test module and the damaged device, Please send your mail ID. I will send email. Here I am not able to do any upload. My admin policy is not allowing this.
 

electric_spd

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I have a suggestion about reason of failure: when you was trying to tune parts of device separately, resistance of second (non used) channel was high. It could cause increasing of S12 and parasitic oscillations. Increasing of output power resulted in increasing of power gain (see datasheet). This explains absence of oscillations at lower output power.

Can you email me photos of test module and damaged device?

My mail ID is electric_spd@mail.ru
 

Boensch

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What a coincidence, we are alsow working on the MRF6VP121KH and have the same Problems with "burned Drains".
Have you solved your problem meanwhile? We've doesn't.
We are using the original Freescale Evaluationboard, with some Modifications for Stability and Bias Gating.

At what Input drive level gets the Transistor Damaged in your application?
Are you also using Bias Gating or do you have constant biasing?
We are assuming, that the Gate is overdriven, but we can not guarantee for a maximum drive level, because we dont reach wanted Output power with significant less drive level.

Selfoscilation wasn't observerd in our case too.

One hint (what wasn't the solution in our case): Some Signal Generators are Producing "false Pulses" in Pulse-Modulation Mode. This is because some Level Measurement Time-Slots (ALC) is done by the Generator. These "False Pulses" had time durations of serveral msecs in our case, what can increases the avg. output-power to critical values.

Regards
Benjamin
 

palanisamy2k

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Hi Boensch,

We also suspecting the problem is with the RF pulse which is driving the PA. In our case the signal Rise time is 5 nS when we burnt a device. After that we tested another device with a low end Signal generator with 40nS rise/fall time. No failure was observed and we finished the design.

The problem again started when we started the modulation in our board. This confirms our suspect ion on Rise time and fall time in the drain breakdown issue.

I am using a SPDT switch from Hittite ( HMC849 ) which is saying 80nS Rise/Fall time. But I am getting rise time of 40nS and fall time of 10nS. I have Burnt more than 10 devices without knowing this fall time issue. Is there any method to slow down the Fall time of the Pulse?
 

tony_lth

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Try to add shunt cap to slow down the rise or fall time.
 

Boensch

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We are using baseband shaped pulses (DAC+2 Mixer Stages) with a risetime of 800ns. But at evaluating state weve used the (almost) rectengular puseles of an rohde@schwarz signal generator. What we have observed, is a "ringing" Voltage at the Drain Voltage feeding rf-choke (about 10 MHz). You Can see it with an ac-coupled scope on the "cold" end of the rf-chocke. Pehaps it helps to damp these resonances by adding several ohms to the midrange blocking capacitors in the lower uF-Range, or change the blocking setup. We are also working on prenting damage. Everything worked fine until we mounted the shielding case...

I dont think it is possible to influence the risetime of an GaAs-SPDT by slowing the control signal. This would work with a PIN-Diode-Switch or voltage variable attenuator, such as HMC473

Regards
Boensch
 

rajtripathi2012

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Hi palanisamy2k,

I am a M.tech student and exploring the possibility of designing a Class AB RF Pulsed power amplifier using freescale LDMOS transistor. Since you have progressed very well in this direction, could you kindly guide me how to go about it. Additionally i wish to ask one more thing, i want to use it for frequency range of 1Mhz - 10 Mhz. Will it perform in this range effectively?

Kindly revert.

Thanks.
 

FvM

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Impedance matching is main challenge with MOSFET wideband amplifiers, You can refer to the Polyfet application notes, they have a large number of example circuits.
 

BorisBJL10

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Hi everybody,

I'm also now being involved with building radar amplifier using Freescale's MRF6VP121KH 1000W transistor. And I'd like to accumulate others' experience in order not to make errors leading to expensive parts blown away.

So my question to both topic starter - Palanisamy2k and Boensch:
Did you complete successfully this amplifier's design, so that part won't fail at rated 1000 W RF power?
If yes, what has turned out be the main issue leading to transistor's death? Was it only rise and fall time of RF switch shaping envelope RF pulse?

I am using a SPDT switch from Hittite ( HMC849 ) which is saying 80nS Rise/Fall time. But I am getting rise time of 40nS and fall time of 10nS. I have Burnt more than 10 devices without knowing this fall time issue.
I can unnderstand rise time reason. But is the fll time that critical too? How can transistor fail when signal is being turned off?

What switch device you both ended up using in final reliable design? MMIC switch or discrete PIN-diode with RC-delayed control voltage to expand rise/fall times?

What do you think of MiniCircuits'
VSW2-33-10W+ ?
It features 150-300 nS rise/fall times, depending on 3-5 V control voltage.

It would be nice to hear from you on your experience with this amplifier.
 

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