Clock recovery (CDR) doesn't work with a standard phase-frequency detectors. It can only refer to the phase of existing edges. That's why it needs a protocol with guaranteed run length, e.g. 8b/10b encoding or withened data.
Xilinx has XAPP250 and XAPP868 dedicated to CDR, other options are by utilizing dynamic phase shift of PLLs (Altera C III and upwards).
Some devices have also a soft CDR option supplied with their hardware SERDES blocks. Hardware CDR is generally available for Gigabit transceivers.