Doubt Regarding Phase Frequency Detector

[anandkumarcr]

Hi,

I am trying to design a clock recovery ckt for a serial input data. I came accross many materials which implement Phase Frequency detectors using the RS Flip Flop
However I am unable to resolve the fact that it needs a reference clock signal in addition to the existing VCO clk.

My requirement is as follows :-
-> I get a random serial binary data in NRZ format. I need to recover the clock from the data.

I am planning to implement a PLL for the clock and data recovery.
The VCO in my case is a simple 32-bit accumulator with the input as the correcting factor.
The output of VCO is M*(F)/(2^32) where F is the base clk I am using and M is the multiplying factor decided by Phase/Frequency Detector

However I do not get any reference signal alongwith my data. In this case how do I recover the clock?
Or detect the frequency difference b/w clock and my VCO clk ?

 

[FvM]

Clock recovery (CDR) doesn't work with a standard phase-frequency detectors. It can only refer to the phase of existing edges. That's why it needs a protocol with guaranteed run length, e.g. 8b/10b encoding or withened data.

Xilinx has XAPP250 and XAPP868 dedicated to CDR, other options are by utilizing dynamic phase shift of PLLs (Altera C III and upwards).

Some devices have also a soft CDR option supplied with their hardware SERDES blocks. Hardware CDR is generally available for Gigabit transceivers.

 

[anandkumarcr]

Hi thank you for the reply.
I am referring to the following data sheet(LVDS Serializer Deserializer 15 - 66Mhz) for my design :-
**broken link removed**

In this data sheet there is no mention of ENDEC(Encoder Decoder) as such. Do they use any proprietary encoding scheme ?
I need to design a clock recovery ckt for the deserialization of the data coming in from an LVDS interface.

Thank you

 

[FvM]

Do they use any proprietary encoding scheme ?

Yes, but if I remember right, it's described somewhere in the datasheets.