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doubt regarding FINFET netlist in HSpice

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anne rachel

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Hello everyone,


Below is a netlist for implementation of drain characteristics of FINFET in HSpice.

X1 1 2 2 0 DGNMOS1

v1 Vdd 0 2.5
v2 Vdd 1 0
v3 vcc 0 1.2
v4 vcc 2 0

.DC v1 0 2.5 .5 v3 0 1.2 .1
.trans 10u 10m
.probe V(*) I(*)
.end


My doubt is if Vdd and vcc aren't defined anywhere before, how is that they are being used in the 2nd to 4th statements? What does
" v1 Vdd 0 2.5" mean??
What does "v3 vcc 0 1.2" mean?




Thanks in advance :)
 

erikl

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Vdd and vcc aren't parameters, but node names.

"v1 Vdd 0 2.5" means a voltage source with name "v1" between the nodes "Vdd" (pos.) and "0" (neg.) with a default value of 2.5V .
(The default value is valid, if v1 is not changed in a SWEEP statement, like this is done in the .DC statement.)
Similar for "v3".
 

anne rachel

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Thanks :) but my question is how does HSpice internally know that v3 is for gate to source voltage when the node "2" which is actually defined as gate in this netlist is not included while defining v3 voltage?Similarly, the drain node "1 " hasn't been mentioned anywhere in the statement that defines "v1" voltage, so, how is that Spice interpreting "v1" as drain to source voltage? I would be grateful if you could clarify this doubt...
 

prestonee

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i do not understand your issue, you define a supply vdd to be 2.5V from gnd. you then define node 1 to be equal to vdd. you next are defining a supply voltage vcc to be 1.2 from gnd. and then define node 2 to be equal to be equal to vcc.
is this what your intent was? that makes your connection line equal to :

X1 2.5V 1.2V 1.2V 0V DGNMOS1

as erikl said you are defining them, there are 4 statements you asked how the 2nd and 4th work without vcc and vdd being defined.. the 1st and 3rd lines are the vdd and vcc defines.. V# 'node1' 'node2' voltage is the basic define of a voltage source.
in spice you do not define nodes(nets)...

-Pb
 

anne rachel

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Thanks a lot prestonee .. I am new to Spice . Sorry, if my doubt was silly. I have clearly understood now.
 

erikl

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Hello prestonee,
this may all be correct, but it possibly could lead to misinterpretation. I try and make it a bit clearer:

... you define a supply vdd to be 2.5V from gnd. you then define node 1 to be equal to vdd. you next are defining a supply voltage vcc to be 1.2 from gnd. and then define node 2 to be equal to be equal to vcc.

Vdd and vcc only are node names (or node designations) only, not voltage definitions!

... you are defining them, there are 4 statements you asked how the 2nd and 4th work without vcc and vdd being defined.. the 1st and 3rd lines are the vdd and vcc defines..

Again: In all 4 lines, Vdd & vcc are only node names, not voltages! I.e. the 4 lines define 4 voltage sources v1 .. v4 .

V# 'node1' 'node2' voltage is the basic define of a voltage source.
Correct! In total ...

... that makes your connection line equal to :
X1 2.5V 1.2V 1.2V 0V DGNMOS1
Absolutely correct!
It means that the gate and the source both have the same voltage of 1.2V referred to bulk=substrate (node 0), i.e. they are virtually short-circuited.

in spice you do not define nodes(nets)...
... because these are defined in the connectivity of the netlist(s), which are combined with the voltage/current source definitions.
 

anne rachel

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Thanks for the detailed explanation erikl :)
But as far as i know,the syntax for the FINFETS connection line is as follows:
Drain Gate_forward Gate_backward Source
So, the two 1.2 V here correspond to Gate_forward and Gate_backward voltages since Finfet is double-gate MOS.

- - - Updated - - -
 
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erikl

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... as far as i know,the syntax for the FINFETS connection line is as follows:
Drain Gate_forward Gate_backward Source
So, the two 1.2 V here correspond to Gate_forward and Gate_backward voltages since Finfet is double-gate MOS.
Yes, you're right. Had forgotten, sorry!
 

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