// Code your design here
module data_sampling_doubt1 (
input clk,
input rst,
input [3:0] data_in,
input vld,
input [1:0] opcode,
output reg [3:0] data_out1,
output reg [3:0] data_out2
);
reg [3:0] data_temp;
always@(posedge clk)
begin
if(rst)
data_out1 <= 0;
else if(vld)
case(opcode)
2'b11: data_out1 <= data_in;
default: data_out1 <= 'hF;
endcase
else
data_out1 <= 'hE;
end
// pipelining the input port data into a data_temp register//
always@(posedge clk) begin
if(rst)
data_temp <= 0;
else
data_temp <= data_in;
end
always@(posedge clk)
begin
if(rst)
data_out2 <= 0;
else if(vld)
case(opcode)
2'b11: data_out2 <= data_temp;
default: data_out2 <= 'hF;
endcase
else
data_out1 <= 'hE;
end
endmodule