Thank you, electronrancher, but, as for the transisent analysis with VDD ramp up, I have another question. Will the step of analysis, like 1ns or 1us or 1ms, affect the result of simulation? And why?
And another question, once, I simulated the self-referenced circuits (without startup circuit) with VDD ramping up at different slope. I found that, though the circuit seems to remain in zero state at first, it would "jump to start" if you increase the Tstop of transisent analysis.