Doubt in VHDL Process statement

[revooridinesh]

Hi

Process(clock)
begin
---
---
---
end process

How to know how much time the above three statements takes to execute ? Because the time they take should be less than half cycle period in order all 3 statements to be executed in one clock change.

Thanks

 

[TrickyDicky]

VHDL is not a programming language. a process executes in 0 time. It will map to logic. So your process will only execute when the clock signal changes.

 

[FvM]

VHDL statements don't take "time to execute" because in the generally case each statement describes independent hardware elements, e.g. registers and combinational logic.

The delay between registers or in- and outputs in a particular data path has to be considered however. VHDL synthesis tools perform timing analysis to guarantee correct operation according to specifications.

 

[revooridinesh]

Thanks Tricky and FvM
Got the point
Do you know any good material where I can study timing analysis in Xilinx.