In SAR ADC, clock for both comparator and the controller should be same if you are going to design synchronous SAR. Each clock has positive level and negative level. Generally at positive edge controller plugged the capacitor and positive lever time is used to settle the voltage. for all this time comparator is in reset mode, so any hangup problem might not occur, because at each comparison it gets reset. At the negative edge comparator goes into comparison, from this time to end of the cycle is allowed to compare. At the beginning of next clock the previous value is latched.
If you use linear feedback shift register, then controlling is easy. Anyway you can check some paper from IEEE or search in google to know the clock timing for a conventional SAR.