doubt in system verilog

[deepu_s_s]

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

 

[aji_vlsi]

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Yes, there are several mini enhancements that are synthesiable and DC does allow them.. Some are:

always_comb, _ff etc.
unique/priority case/if
enumerated types
Interface

Not an exhaustive list above, but point is YES

Ajeetha, CVC
www.noveldv.com

 

[deepu_s_s]

hi ajitha!


so can i use Synopsys DC as a synthesis tool for System verilog

 

[shiv_emf]

yes deepu U can use DC for synthesis
but few features(constructs) in system verilog cannot be synthesized !!.......

 

[deepu_s_s]

hi shiv!

can u gimme some example features?

thx
deepu

 

[satyakumar]

HI deepu,
The following features are not synthesizable.
1) unpacked unions
2) variable declarations in packages
3) static functions and tasks declared in packages
4) two state logic variables has some problem during synthesis

 

[atuo]

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Hi ,

I think the verilog-2001 is including in system verilog, so you can say we can use system verilog for synthesis.

But by now, system verilog is mainly used for HVL.

Thanks.

 

[satyakumar]

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Hi ,

I think the verilog-2001 is including in system verilog, so you can say we can use system verilog for synthesis.

But by now, system verilog is mainly used for HVL.

Thanks.

I think there are lot enhancements to verilog-2001 in system verilog, its very comfortable at system level modeling. Regarding HVL its built in advantage of systemverilog.

 

[deepu_s_s]

thx to all of u . u cleared my doubts