Doubt in deep nwell structure

[Yathin P U]

In mixed signal ckts there is only an imaginary line to seperate the Digital and Analog parts.The SUB is common for both ,digital ckts usually operate at higher frequencies so thet switch on and off at very faster rate.They dump minority charge carriers in the SUB which can affect the analog nmos's behaviour.so there is a need to protect analog nMos transistors form this sub noise so there is a concept of Deep N Wells.Plz check the attachment to get the exact picture of Deep N Well..this is not the case with pMOS because we draw p MOS transistors in n Well

(this quote is taken from the thread with title " DEEP nwell for negative voltages")

In the above mentioned quote Mr. Vivek has said about digital circuits dump minority charge carriers in the sub. Can anyone please eloborate on this?

Thanks

 

[erikl]

nMOS sources inject electrons mainly into the inverted channel, but a small part of them arrive as minority charge carriers at the substrate. Depending on their life time, they can stroll away and arrive at other devices, if not caught by an n⁺ guard ring or a deep nwell.