[SOLVED] doubt about open collector/drain using in i2c

[PRABAKARDEVA]

Why some pins are used as open collector/drain in microcontrollers?


Why open drain is used in i2c?


Can anyone reply.pls...

 

[andre_luis]

Why open drain is used in i2c?

Open drain output at I2C devices allow insertion of multiple ones at the same communication bus, due no severe hardware conflict will occur, even if performed an incorrect mutual addressing.


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[Gorgon]

This is called a wired-OR configuration. Only the LOW condition is an active output, where the open drain sink the signal to 0V.
This way there is no danger for a collision between HIGH and LOW, resulting in a short Circuit.
Reading the status there is also no problem With a logical collision, since the unit expecting a HIGH, will know there is a logical collision if it is reading a LOW, and stop it's transmission. This way the unit With the LOW will 'win' and no error is resulting in the transmission.

 

[PRABAKARDEVA]

This is called a wired-OR configuration. Only the LOW condition is an active output, where the open drain sink the signal to 0V.
This way there is no danger for a collision between HIGH and LOW, resulting in a short Circuit.
Reading the status there is also no problem With a logical collision, since the unit expecting a HIGH, will know there is a logical collision if it is reading a LOW, and stop it's transmission. This way the unit With the LOW will 'win' and no error is resulting in the transmission.

sorry Gorgon...i couldn't understand..could you explain it briefly please?

 

[Gorgon]

What part of it did you not understand? Give me a hint and I'll try to expand on it.

 

[DNA Robotics]

I have a 5v PIC and a 3v accelerometer module with pull-ups on board. Open collector lets them work together without conflict.

 

[betwixt]

Imagine you have two devices (or more) on the same connection (clock or data, it doesn't matter) and one is driving high while the other is driving low. Instead of a recognizable logic level, you get current flowing out of one device into the other with the risk that both are overloaded. In an open collector/drain configuration there are no devices driving high, the logic '1' comes from current through the pull-up resistor and it's value is chosen to keep the current low enough that devices are not damaged. Devices can only pull the line low and if by accident or design, two devices drive low at the same time, no harm is done.

Advantage = lots of devices can share the same connection.
Disadvantage = It forms an RC network with the pull-up being 'R' and the capacitance of the wiring and devices being 'C' so it is slower to react than a normal logic connection. More devices on the bus or higher value pull-up resistance make it slower. For many applications the speed is still fast enough though.

Brian.

 

[chandu.kurapati]

Hi every one,
My doubt is when two devices are compete for same I2C Bus, in that according to arbitration mechanism one device won the bus access, another one last.

imagine when one device at high level , another one at low level on the I2C bus, then how I2C bus manage this two states at a time? there any special feature for I2C Bus?

Please explain me about the condition and what is the wired or significance in I2C?

Thanks & regards,
Chandu.Kurapati.

 

[Gorgon]

Well, when two devices compete on the bus, the device that put out the 'low' signal always win. The reason is that any device can only actively put out a 'low'. The 'high' is only present when all devices either are off the bus, or want to send a 'high'.

With an open drain output, you need a pullup resistor to +Vdd, to get a 'high'. 'High' is then only present when ALL devices does NOT pull down. The 'low' is present when one, or more devices actively pull down the line.

 

[chandu.kurapati]

Hi everyone,

My intention is when the two devices start communication on the I2C bus at the exactly same time, what will be happen?

please explain me.

Thanks & Regards,

Chandu.Kurapati.

 

[Gorgon]

This is answered in post #3 and #9. Please read these.

 

[chandu.kurapati]

Hi Gorgon,
Thank you, i understand the your 3rd and 9th post. can you please explain about wired OR connection in detail.

Thanks & Regards,
Chandu.Kurapati.

- - - Updated - - -

Hi every one,
In the I2C protocol, two devices driving the I2C bus to low at a time is possible? please explain me?

Thanks & Regards,
Chandu.Kurapati.

 

[betwixt]

Wired OR is the same as the logic OR function but with multiple devices on one line.

Like the logic function, the output is low when one input or another input or both are low. In other words, the only high condition is is none of the devices are pulling the line low.

Brian.

 

[chandu.kurapati]

Hi every one,
In the I2C protocol, two devices driving the I2C bus to low at a time is possible? please explain me?

Thanks & Regards,
Chandu.Kurapati.

 

[Gorgon]

Please read this thoroughly, it should answer all your questions: Wikipedia on I2C

 

[PRABAKARDEVA]

what is the working of wired or configuration?

can i use wired and configuration?does any changes applicable?

 

[betwixt]

What don't you understand?

It is exactly the same logic as a conventional OR gate except the devices on the node cannot drive the wire high. The pull-up resistor does that instead.

Yes, there is a wired AND equivalent but it is seldom used because it offers no advantage over conventional gates.

To answer your earlier question, in a wired OR configuration there can be many devices capable of driving the bus but only one can communicate over it at a time. The way it works is before pulling the line low, the device checks to see if it is already in use by 1. seeing if the line is already low and 2. monitoring start and stop signals on the bus to ensure another device isn't in mid-message.

Brian.

 

[Gorgon]

Technically it is a wired AND connection, if that was your question, since when all signals are high, the result is high (idle). The functionallity is the same whatever you call it. Active condition is LOW, idle condition is HIGH.

I suppose you know that the signals are inputs at the same time as they are outputs.