Doubt about de-asserting a reset and generating a peripheral clock

[prabhu.er]

Dear All,

In Digital Circuit Design When we de-assert the reset signal.

What happen before the clock oscillating we de-assert the reset. that is reset is de-asserted but till clock is did not come from clock generator ( clock is generated by internal clock generator). In board level how this design work. If any problem arise due to this help me.

Regards,
Prabhu

 

[asicdesigner]

reset clock

Depends on how the logic is designed. If you are synchronizing the reset to use synchronous reset in your design, the synchronization of reset will delayed until the clock arrives and also the output data from the FFs. If you are using asynchronous reset, only the output data will be delayed until the clock arrives.

In either case, I don't see any issues. Usually on board enough time is given between assertion and de-assertion of reset before starting normal operation.

 

[sachin_kirdat]

generated clock reset

think of start up time of oscillator

Added after 15 seconds:

jitter and unstable clk

 

[vlsi_freak]

clock reset design

From your question, i guess there is no issue as such in board level.
Can you make your question more clear, the background of this doubt

regards,
freak

 

[prabhu.er]

reset assertion and de-assertion

Ok, Now I try to explain clearly about my doubt.

Just One processor it is working under 300MHz. This Processor is interfaced with one peripheral.

Processor and peripheral both have same reset called sys_rst_n (active low). So, whenever processor reset is de-asserted peripheral reset also de-asserted.

Processor have clock called as "sys_clk". peripheral clock called as "p_clk". For power saving purpose p_clk is generated (using internal clock divider circuit, source clock is sys_clk) and send to the peripheral whenever need to use otherwise p_clk is zero.

my doubt is what happen in peripheral logic during after sys_rst_n de-assertion and before the p_clk generation.

This is allowable in design and it cause any problem in board work or silicon.

 

[skyfaye]

Re: Clock Vs Reset

I think this should not pose any issues. Basically the peripheral is out of reset and ready but it does not have an active clock. So it really is in a disable state. Assuming the processor is the only device that controls it, the peripheral only need to be in enable state whenever processor need to talk to it. Since the processor give it an active clock to wake it up, everything should be fine.

- Hung

 

[prabhu.er]

Re: Clock Vs Reset

Thank you very much to all

Now I got clear idea.