reset clock
Depends on how the logic is designed. If you are synchronizing the reset to use synchronous reset in your design, the synchronization of reset will delayed until the clock arrives and also the output data from the FFs. If you are using asynchronous reset, only the output data will be delayed until the clock arrives.
In either case, I don't see any issues. Usually on board enough time is given between assertion and de-assertion of reset before starting normal operation.