don't care condition coming in every case I give HIGH...why?

[syedshan]

Hi.


Note that It is a test bench and in_cmd is the signal suffering When I want to make it High, it gets Dont care.why?

COMPONENT data_gen_top
PORT(
clk, rst : IN std_logic;
cmd_in_UI : IN std_logic_vector(2 downto 0);
phy_init_done : in std_logic;
in_cmd : in std_logic_vector(1 downto 0); --bit 1 : valid command, bit 0 command itself
..
..
signal in_cmd : std_logic_vector(1 downto 0) := "00";

wait for clk_period*10;
in_cmd <= "10";

wait for clk_period*2;
in_cmd <= "00";


...

Best
Shan

 

[mrflibble]

Going by the testbench screenshot you get X's on in_cmd[1], and in_cmd[0] always stays at 0.

If you change things to:

signal in_cmd : std_logic_vector(1 downto 0) := "10";

Does the problem then suddenly shift to when you do in_cmd <= "00";

All I can think of is that your assignment causes a conflict. But I really should pay more attention to those VHDL classes I never had. I don't really know. I would guess it's a conflicting signal assignment...

 

[syedshan]

doing this it becomes X0 at start then 00 then again x0
where x is the location where '1' should be

 

[mrflibble]

As suspected. So it really does look like a conflicting assignment.

You're driving in_cmd[1] with two drivers. As long as they are equal it's no problem and you get a logic value. The moment the two drivers are different the simulator gives you the simulator equivalent of "Screw you hippie!" and you get an X.

I guess you could do something like this:

signal in_cmd : std_logic_vector(1 downto 0) ;

That way you should only have 1 driver per signal.

 

[K-J]

doing this it becomes X0 at start then 00 then again x0
where x is the location where '1' should be

Since you likely have multiple processes driving in_cmd as mrfibble suggests, here is a simple debug method to locate the drivers
- At the Modelsim prompt (assuming you're using this tool), type 'drivers in_cmd' and it will return the list of drivers for the signal as well as what each driver is trying to drive the signal to.

Now if you want to avoid having to debug such errors, consider using std_ulogic_vector (and std_ulogic) rather than std_logic_vector (and std_logic). Now when you simply compile the source code or, at the latest, when you start the sim, the simulator will complain right then and there about the multuple drivers and not let you go on. Much easier to fix the error that way then having to debug to find it. Save your use of std_logic_vector (std_logic) for those signals which truly do have multiple drivers by design such as a bi-directional bus. Most signals in a design and testbench are not that type of signal.

Kevin Jennings

 

[TrickyDicky]

As a point of reference - 'X' is unknown, not dont care. '-' is dont care.

 

[syedshan]

Thank you for all replies.

But in_cmd signal is the input to the entity under test, where as in the testbench it is just driven by 1 driver. As I told above I also tried to just initialize it withou any driver as

signal in_cmd : std_logic := "10";

but same result...
This is first time I have seen so was curious, also cannot do simulation as well.

 

[TrickyDicky]

why not post the testbench code- and we'll give our opinions?

 

[syedshan]

Hi

Thank you for all your inputs...:roll:
I started things fresh today and it worked fine...
I really did not do anything new. just the same code but started all over again.

Thanks all...