Vonn
Full Member level 4
Iam using XC95216 CPLD and when I wrote my code on ISE and try to synthesize I put a constrain on the master clock used to be 100 MHz ; the sythesizer didn't give me error but the timing report showes that maximum performance frequency is 27 MHz ; at the same time it told me that ( All constrains were met ) my question is
Does the performance frequency differs from the master system clock used
Does the performance frequency differs from the master system clock used