A counter is a chain of; async ripple counters or sync flip-flops . A PLL phase comparator is only an XOR gate with a VCO, so has fewer gates.
The counter method requires high CNR from narrowband BPF to prevent glitches and extra or missing counts.
Group delay distortion of the channel filter andSNR will limit bit rate.
A detector which integrates all of the signal energy over the bit interval with a receiver bandwidth matching that signal content, will give the performance of an ideal "Matched Receiver"
once the clock is phase locked, the integrator can be dumped or initialized and start integrating the phase error all over again to determine the next bit. However typical tpe II detectors use Pump up/ Dn output that otherwise float or hold until next bit intervalphase meaurement to generate the VCO error voltage.
The integration of a step in frequency (FSK) is a ramp in Phase rate of change.
Synchronous detection is ideal for both ASK and FSK using integrate and dump relative to the reference (AGC amplitude or PLL frequency )
But both can and have been done with or without synchronous detection. FSK once used the edge of a BPF to detect amplitude shift with frequency and no clock required.
a "matched receiver" is preferred for SNR < 20.
For FSK there is a signal improvement factor from carrier deviation ratio. So from CNR to SNR , improvement increases with log of deviation ratio.
what are your channel specs for signal and, noise?