If poly gate contact is allowed over active then active-
active min spacing might set the distance between "bars".
If contact must be outside active then spacing would be
probably poly-poly defined, with active-active spacing
being poly-poly+2*contact-active.
At some point (which you may be unable to determine)
a given active to active real (as opposed to rule) spacing
looks "enough like" open field, as far as litho loading
effects go. And this is what dummies are meant to address.
Dummies could be less W than the "real deal" FETs. How
much is enough, again may not be known. Maybe a couple
contacts' worth of width, something above min but less
than the "real deal" FET W might be a good tradeoff. Of
course you could go full replica if you were not in an area
sensitive situation. But who gets that luxury other than
test chip designers, or folks working on I/O-limited SSI
stuff?