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Cadence does not.. However I have seen some VERY fancy overlays.
Here is how you can do it with existing licences...
1) Roughly redraw the cavity & pkg-pins in cadence or get gds file of package.
reference chip in pkg drawing. Use ruler (any-angle) to get distance and look for
crossed wires. As far as R/C/I it is just math from there.
2) print bonddiagram and plot to scale the chip.
Then draw your own bondwires.
3) some bond-houses give gdsII files of their pkgs.
This is the best method. Import to ICFB and calculate from there..
Good luck !!
p.s. I've dona alot of this kind of work..
Our CAD group has one guy who will take your bond
diagram (Cadence layout, our PDK assigns a layer to bond
wire) and run it through a 3-D EM solver and spit you
back out a package model including the wires.
I am absolutely certain we wouldn't bother if Cadence
had a believable, reasonably priced (you didn't expect it
as part of a full featured, high priced layout tool, did you?) option.
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