Does anyone know how to measure failure rate in hspice

[niceguyford]

Hi all, I am simulating and evaluating performance of sram cells, and need to scale VDD and transistor sizing. However, all these are based on the comparison in a same failure rate for each schemetic. I had built up the cells. But I don't know how to establish the failure rate or a rate thing in hspice.

Anyone can help or give me some advice?

Thank you all!

 

[erikl]

May be your wording failure rate is a bit confusing within this forum? Failure rate usually concerns failure in time, i.e. malfunction during operating life time. Do you mean this failure rate? If so, hspice is the wrong tool.

If you, however, think of wafer yield, i.e. percentage of good chips on a wafer, hspice MC (Monte Carlo) analysis could provide you an answer - if you get the proper parameters from your foundry.

 

[niceguyford]

May be your wording failure rate is a bit confusing within this forum? Failure rate usually concerns failure in time, i.e. malfunction during operating life time. Do you mean this failure rate? If so, hspice is the wrong tool.

If you, however, think of wafer yield, i.e. percentage of good chips on a wafer, hspice MC (Monte Carlo) analysis could provide you an answer - if you get the proper parameters from your foundry.

Thank you so much! Can I have some more detailed knowledge? I am a starter.

As for the first case, failure in time is the required parameter, which software would be the proper tool?matlab or what?

As for the second case, which parameters are needed and how to realize?

Thank you!

 

[erikl]

Can I have some more detailed knowledge? I am a starter.

As for the first case, failure in time is the required parameter, which software would be the proper tool?matlab or what?

Usually, a simple calculator will do the job. Search the net for failure rate or FIT. Here's a starter for a starter ;-)

As for the second case, which parameters are needed and how to realize?

Foundries (should) provide (mis)matching parameters for their processes, which permit the calculation of Pelgrom mismatch of adjacent devices, e.g. Δβ/β for BJTs, and ΔVt/Vt for MOSFETs. The standard equation for such mismatch is σ(Δx/x)[%]=Ax/√Area , where σ means (1) standard deviation for the Δx/x mismatch, Ax is the respective parameter to be provided by the foundry for their process, given in [%µm], x the respective parameter whose mismatch is to be evaluated (β, Vt, ...), and Area is the area of adjacent devices, whose mismatch is to be calculated.

Moreover, foundries sometimes provide mismatch parameters for remote devices (i.e. non-adjacent, being "far" from each other), which are Ax parameters not dependent on (Pelgrom) device area, but on device distance, also given in units of [%µm]. The √Area denominator in the equation above will be replaced by the distance [µm] in this case.

in this forum.