Ouch!
OK, I am not an expert on analogue but I try to explain.
Yes, the transition time of cell depends on input transition time and output load. Assuming the input transition time is Ti and output load is Lo, the transition time of a cell is
T(up)=G(up)*Ti(up)*Lo and T(down)=G(down)*Ti(down)*Lo (we have used two assumptions here, 1. the equation is simplified into linear 2. up input caused a positive output)
The G here depends on the cell structure, in detail, is the density of P and N doping and the area of the doping region. The G itself means the amplify factor of input voltage to output current.
Unfortunately, the G for P Mos and N mos are different so normal CMOS transistors have different open and shut down time, which is the source of different up and down transition time.
By carefully compensation and match of the amplification factor, G, the balanced CMOS cell have similar G for PMOS and NMOS. Therefore, in most conditions, G(up) == G(down).
Supposing all cells in a clock tree have G(up) == G(down), a direct consequence will be Ti(up) == Ti(down). And finally T(up) == T(down).
In other words, although transition time depends on input transition and output load, as long as the G of PMOS and NMOS is equal, the positive edge transition and negedge transition will be the same. The transition time of a cell is not a fixed value but T(up) == T(down) in a balanced cell.