Documents on level-shift circuit design

[yutian]

Hi, I want to design a level-shift circuit recently(5v-24v). Who has some paper or article, circuit?
Thanks a lot

 

[pfd001]

level shifter 24v

Is it digital signal or analog signal

 

[freetofree]

24v 5v level converter circuit

charge pump?

 

[venky442]

logic level shifter 24v

Hi,
do u want to design a level up or down shift circuits which can be useful in SOC applications with only sinlgle mail power supply.
u can get these papers from IEEE with level shift circuits as the head line in the search box.

these can reduces the no of interconnects and complexity.

 

[runblade]

maxim level shift 5v 24v

Hi, Give a look to step-up circuits (buck boost typology) from several semiconductors manufacturer (TI,Linear,Maxim,National,etc.)

 

[Sadegh.j]

5v to 24v level shifter

Are you looking for a simple DC-to-DC Boost converter by any chance?

 

[liuyonggen_1]

24v level shifter

what's application for this kind of level-shift?
In my opinion, in soc design, level-shift is the brige of analog voltage and digital voltage.

 

[yutian]

level shifter 24v 5v

Thanks all.
I want to design a level up shift circuits(5V-24V). In the circuit, the rising time and fall time are very short (<40ns).
Anyone have some paper or aiticle?

 

[ameed]

level shifter rise fall -patent

Hi,

do you want to design a level up or down shift circuits which can be useful in SOC

applications with only sinlgle rail power supply.

you can get these papers from IEEE with level shift circuits as the head line in the search box.
there is a EDACAFE.COM in which you can getting papers.

these can reduces the no of interconnects and complexity.

thanx......

 

[ambreesh]

levelshift down with enable

You want a simple level shifter that would take your signal which is (0,5) to a signal that is (0,24).
I hope my understanding is correct.

Have 2 crosscoupled PMOS connected to the 24V supply.
Have 1 NMOS below each.
The sources of the NMOS are connected to vss.
One of the NMOS is driven by the 5V signal and the other is driven by its inverted signal.

Take care that the devices you use for PMOS can handle 24V on their gates or are 24V compatible.
Also the NMOS have to be same as one of them would see 24V at its drain. Else you would have to use some cascode devices to protect the NMOS.
Make you NMOS stronger than PMOS as PMOS would have stonger drive than NMOS.

 

[DenisMark]

signal level shifter from 24v to 5v

In addititional to ambreesh's post i provide u some papers and links to papers about digital levelshifter circuits (aka differential logic):





There are many free avaliable US patents also.

The main rule of thumb the high voltage side cross coupled pair must have lower driving capability than low voltage side MOSFETs for all PVT corners. Keep MOS's sizes small to decrease propagation delays and rise/fall times. Take care with reability of MOSFETs.

Don't forget push "helped me" button if my help is usefull.

 

[yutian]

Level-shift circuit

thanks all.
Recently i have downed some paper and studyed the principle of level shift.
In our circuit, we care the level-shift rising time, falling time, area, leakage current.

 

[yutian]

Level-shift circuit

Thabks to all.
I have done the level-shift citcuit and the audio amo and dc-dc converter.

 

[northeast1]

Re: Level-shift circuit

Hi, I want to design a level-shift circuit recently(5v-24v). Who has some paper or article, circuit?
Thanks a lot

cross couple structure

 

[shaq]

Level-shift circuit

If I want to design a level-shift circuit having low input voltage (eg. 0.85v shift to 2.5v), the cross-couple structure can not be used in this situation.

How to design a level-shift circuit to work in low input voltage?

 

[ljy4468]

Level-shift circuit

shaq// why that's not possible??

 

[shaq]

Re: Level-shift circuit

shaq// why that's not possible??

Because clk and clkb (inverted signal) is needed in cross-couple-typed level shifter.
0.85v is too small to pass a inverter.

 

[supreet_95]

Level-shift circuit

can use cross_coupled pmos latch topology placed above two differential nmos structures with (complimented inputs). U can put a series enable switch in series of both path, so that when the input power supply goes away, the floating inputs wont cause high currents in 2nd stage and the series switch can be swithed off.
Hope this helps.