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do u want to design a level up or down shift circuits which can be useful in SOC applications with only sinlgle mail power supply.
u can get these papers from IEEE with level shift circuits as the head line in the search box.
these can reduces the no of interconnects and complexity.
You want a simple level shifter that would take your signal which is (0,5) to a signal that is (0,24).
I hope my understanding is correct.
Have 2 crosscoupled PMOS connected to the 24V supply.
Have 1 NMOS below each.
The sources of the NMOS are connected to vss.
One of the NMOS is driven by the 5V signal and the other is driven by its inverted signal.
Take care that the devices you use for PMOS can handle 24V on their gates or are 24V compatible.
Also the NMOS have to be same as one of them would see 24V at its drain. Else you would have to use some cascode devices to protect the NMOS.
Make you NMOS stronger than PMOS as PMOS would have stonger drive than NMOS.
In addititional to ambreesh's post i provide u some papers and links to papers about digital levelshifter circuits (aka differential logic):
There are many free avaliable US patents also.
The main rule of thumb the high voltage side cross coupled pair must have lower driving capability than low voltage side MOSFETs for all PVT corners. Keep MOS's sizes small to decrease propagation delays and rise/fall times. Take care with reability of MOSFETs.
Don't forget push "helped me" button if my help is usefull.
can use cross_coupled pmos latch topology placed above two differential nmos structures with (complimented inputs). U can put a series enable switch in series of both path, so that when the input power supply goes away, the floating inputs wont cause high currents in 2nd stage and the series switch can be swithed off.
Hope this helps.