Hi Sharkies,
My point of view is that this issue is only a question of tradeoff: parasitic capacitances (your frequency specification), area and better matching. I mean, only if you have difficulty to achieve your frequency requirements, you should avoid the centroid common configuration.
I have seen many designs done using 65 nm, 90 or 135 nanometer CMOS technologies, and all of them uses common centroid layout configuration; for example: amplifiers, references, comparators and data converters.
While the transistors dimensions are scaling down, you know that the size of transistors in analog designs (at least part of them) is not directing following this tendency. For example, while using 90 nm tech., it is often using transistor length of 1, 2 or 3 um.
What I would do is to verify the variability of these circuits using Monte Carlo Analysis. This simulation ignores the layout techniques and shows the worst case performance (1, 2, 3 or 4 sigma requirements). So, if your circuits are working in those simulations, I would not be worry about changing those circuits now.
Regards,