Do FPGA tool list down fan-in and fan-out counts of all internal nets?

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Sumathigokul

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Hi all,

Have a nice day !!

I may implement my digital design using FPGA. Once the design is synthesized, i may read the HDL netlist file to introduce some design modifications, but i want to insert the logic at high fan-in and also high-fanout internal nets. In this regard, i want to know "is there any FPGA design tools which list down the fan-in and fan-out counts of each internal nets of the design." So that, i can refer those report to decide on which nets need to be modified.

Thanks in advance.
 

If you meet your timing requirements - why do you bother manually adjusting fan-outs ?
 

my intention to modify the internal nets was not to adjust the fan-outs.. it is introduce some control logic inside my design at appropriate place which is the fan-in and fan-out net.
 

So do it on the RTL level - I.E: change the code itself.
 

Can you kindly elaborate on how to find out the signal that will have high fan-out once its synthesized?? i.e. it will have high fan-in i.e. input logic cone and high fan-out i.e. output logic cone???
 

Altera Quartus lists high fan-out nets in fitter report.
 

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